In recent years there has been remarkable progress on FPGA, and with the large scale number of gates on mass-produced types. The lengthening of evaluation and verification times to activate the normal operation of FPGA is seen as problematic and has become a serious obstacle for time to market in product development.
In our FPGA design quality improvement services, we consider a variety of aspects of FPGA development, including automatic RTL generation from specifications, verification item extraction and simulation, performance assessment, CDC verification of asynchronous circuits, and streamlining debug of firmware using verification platforms.
By inputting specifications in our specific format, top-connected RTL and register are automatically generated.
We support both short TAT (Turn Around Time) and quality in FPGA design.
*We plan to release assertion and generation of the various UCF files for FPGA development tools in the near future.
We improve the FPGA design quality with SoC verification methodology in the FPGA design. Also, by using generated test benches, we can evaluate performance and make early determination of specifications.
There are a variety of problems that can occur with asynchronous circuits, such as metastabe, reconvergence problems, data loss problems, and etc. When these problems occur, the causes are difficult to be analyzed due to irregularity and irreproducibility of these problems. As a result, they can have a significant impact on development schedules.
Because we perform formal verification, we can solve asynchronous circuit problems without simulation.
For customers who cannot purchase expensive formal verification tools, we perform asynchronous circuit (CDC) verification to verify the locations that violate synchronization rules, making it possible to resolve problems at the design stage.
We can accelerate firmware development by using a firmware verification platform to perform co-verification of hardware and software.
We prepare a simulation environment to verify firmware with real equipment response, so the board evaluation time can be dramatically shortened.
We support both SystemC and SystemVerilog.